View IR3086AMPBF_8924912.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ir3086apbf page 1 of 33 may 13, 2009 data sheet xphase tm phase ic with ovp, fault and overtemp detect description the ir3086a phase ic combined with an ir xphase tm control ic provides a full featured and flexible w ay to implement power solutions for the latest high pe rformance cpus and asics. the ?control? ic provides overall system control and interfaces with any numb er of ?phase? ics which each drive and monitor a si ngle phase of a multiphase converter. the xphase tm architecture results in a power supply that is sma ller, less expensive, and easier to design while providing hig her efficiency than conventional approaches. features 2.5a average gate drive current loss-less inductor current sense internal inductor dcr temperature compensation programmable phase delay programmable feed-forward voltage mode pwm ramp sub 100ns minimum pulse width supports 1mhz per-ph ase operation current sense amplifier drives a single wire avera ge current share bus current share amplifier reduces pwm ramp slope to ensure sharing between phases body braking tm disables synchronous mosfet for improved transient response and prevents negative output voltage at converter turn-off ovp comparator with 150ns response phase fault detection programmable phase over-temperature detection small thermally enhanced 20l mlpq package application circuit dac rphase3 ccs+ 20k rbiasin bias cvccl rcs+ ramp l cpwmrmp rvcc dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic ccs- ishare rpwmrmp cscomp ea cbst vo co vrhot phase fault 12v dbst vgate 5 wire analog bus from control ic cvcc rcs- rphase1 rphase2 cin downloaded from: http:///
ir3086apbf page 2 of 33 may 13, 2009 ordering information device order quantity ir3086amtrpbf 3000 per reel * IR3086AMPBF 100 piece strips * samples only absolute maximum ratings operating junction temperature?????..150 o c storage temperature range???????.-65 o c to 150 o c esd rating???????????????hbm class 1c jedec standar d pin # pin name v max v min i source i sink 1 rmpin+ 20v -0.3v 1ma 1ma 2 rmpin- 20v -0.3v 1ma 1ma 3 hotset 20v -0.3v 1ma 1ma 4 vrhot 20v -0.3v 1ma 30ma 5 ishare 20v -0.3v 5ma 5ma 6 scomp 20v -0.3v 1ma 1ma 7 eain 20v -0.3v 1ma 1ma 8 pwmrmp 20v -0.3v 1ma 20ma 9 lgnd n/a n/a 50ma n/a 10 vcc 24v -0.3v n/a 50ma 11 vccl 27v -0.3v n/a 3a for 100ns, 200ma dc 12 gatel 27v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 13 pgnd 0.3v -0.3v 3a for 100ns, 200ma dc n/a 14 gateh 27v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 15 vcch 27v -0.3v n/a 3a for 100ns, 200ma dc 16 csin+ 20v -0.3v 1ma 1ma 17 csin- 20v -0.3v 1ma 1ma 18 phsflt 20v -0.3v 1ma 20ma 19 dacin 20v -0.3v 1ma 1ma 20 biasin 20v -0.3v 1ma 1ma downloaded from: http:///
ir3086apbf page 3 of 33 may 13, 2009 electrical specifications unless otherwise specified, these specifications ap ply over: 8.4v v cc 14v, 6v v cch 25v, 6v v ccl 14v, 5.9v v(biasin) 7.1v, 0.8v v(dacin) 1.6v, and 0 o c t j 125 o c, c gateh = 3.3nf, c gatel = 6.8nf parameter test condition min typ max unit gate drivers gateh rise time vcch = 12v, measure 2v to 9v transition time 22 50 ns gateh fall time vcch = 12v, measure 9v to 2v transition time 22 50 ns gatel rise time vccl = 12v, measure 2v to 9v transition time 50 75 ns gatel fall time vccl = 12v, measure 9v to 2v transition time 50 75 ns gatel low to gateh high delay vcch = vccl = 12v, measure the time from gatel falling to 1v to gateh rising to 1v 10 25 50 ns gateh low to gatel high delay vcch = vccl = 12v, measure the time from gateh falling to 1v to gatel rising to 1v 10 25 50 ns disable pull-down current force gateh or gatel = 2v with biasin = 0v 15 25 40 a current sense amplifier csin+ bias current -0.5 -0.25 0 a csin- bias current -1 -0.4 0 a input offset voltage csin+ = csin- = dacin. measure input referred offset from dacin -3 0.5 5 mv gain at t j = 25 o c 32 34 36 v/v gain at t j = 125 o c 27 29 31 v/v slew rate current sense amplifier output is an internal node. slew rate at the ishare pin will be set by the internal 10k resistor and any stray external capacitance 12.5 v/ s differential input range -20 100 mv common mode input range -0.2 4 v rout at t j = 25 o c 7.9 10.5 13.1 k rout at t j = 125 o c 9.3 12.4 15.5 k ramp comparator input offset voltage 20 40 80 mv hysteresis note 1 20 40 80 mv rmpin+, rmpin- bias current -3 -1 1 a propagation delay vcch = 12v. measure time from rmpin input (50mv overdrive) to gatel transition to <11v. 100 150 240 ns percentage of common mode input voltage range v(rmpin+) / v(biasin) or v(rmpin-) / v(biasin) 7 70 % downloaded from: http:///
ir3086apbf page 4 of 33 may 13, 2009 parameter test condition min typ max unit ramp discharge clamp clamp voltage force i(pwmrmp) = 500 a. measure v(pwmrmp) ? v(dacin) -10 5 20 mv clamp discharge current 4 8 ma pwm comparator pwm comparator input offset voltage -5 5 15 mv eain & pwmrmp bias current clamp and current share adjust off -1 -0.4 1 a propagation delay vcch = 12v. measure time from pwmrmp input (50mv overdrive) to gateh transition to < 11v. 70 150 ns common mode input range exceeding the common mode i nput range results in 100% duty cycle 5 v share adjust error amplifier input offset voltage 10 20 30 mv input voltage range eain ? pwmrmp, note 1 -3.5 3.5 v pwmrmp adjust current 4 8 ma transconductance i(pwmrmp) = 3.5ma, note 1 0.9 1.6 2.3 a/v scomp source/sink current note 1 20 30 40 a scomp activation voltage amount scomp must increas e from its minimum voltage until the ramp slope adjust current equals = 10 a 60 150 300 mv pwmrmp min voltage i(pwmrmp) = 500 a 150 225 350 mv body braking comparator threshold voltage compare to v(dacin) 88 91 94 % propagation delay vccl = 12v. measure time from eai n < 0.91 x v(dacin) (200mv overdrive) to gatel transition to < 11v. note 1. 100 150 ns ovp comparator threshold voltage compare to v(dacin) 100 125 160 mv propagation delay vccl = 12v. measure time from csi n > v(dacin) (200mv overdrive) to gatel transition to <11v. 150 250 ns phase fault comparator threshold voltage compare to v(dacin) 88 91 94 % output voltage i(phsflt) = 4ma 300 400 mv phsflt leakage current v(phsflt) = 5.5v 0 10 a vrhot comparator hotset bias current -2 -0.5 1 a output voltage i(vrhot) = 29ma 150 400 mv vrhot leakage current v(vrhot) = 5.5v 0 10 a threshold hysteresis t j 85 o c 3.0 7.0 9.0 o c min typ max threshold voltage t j 85 o c 4.73mv/ o c x t j + 1.176v 4.73mv/ o c x t j + 1.241v 4.73mv/ o c x t j + 1.356v v downloaded from: http:///
ir3086apbf page 5 of 33 may 13, 2009 note 1: guaranteed by design, but not tested in productio n pin description parameter test condition min typ max unit general vcc supply current 10 14 ma vccl supply current 2.5 5 ma vcch supply current 6v v cch 14v 5.5 8 ma 14v v cch 25v 6.5 10 ma biasin bias current -5 -2.5 2 a dacin bias current -2 -0.5 1 a pin# pin symbol pin description 1 rmpin+ non-inverting input to ramp comparator 2 rmpin- inverting input to ramp comparator 3 hotset inverting input to vrhot comparator. conne ct resistor divider from vbias to lgnd to program vrhot threshold. diode or thermistor may be substituted for lower resistor for enhanced/remote temperature sensing. 4 vrhot open collector output of the vrhot comparat or which drives low if ic junction temperature exceeds the user programmable limit. co nnect external pull-up. 5 ishare output of the current sense amplifier and input to the share adjust error amplifier. voltage on this pin is equal to v(dacin) + 34 * [v (csin+) ? v(csin-)]. connecting ishare pins together creates a share bus enabling c urrent sharing between phase ics. the share bus is also used by the control ic f or voltage positioning and over- current protection. 6 scomp compensation for the current share control loop. connect a capacitor to ground to set the control loop?s bandwidth. 7 eain pwm comparator input from the error amplifie r of control ic. both gate driver outputs drive low if the voltage on this pin is les s than 91% of v(dacin). 8 pwmrmp pwm comparator ramp input. connect a resis tor from this pin to the converter input voltage and a capacitor to lgnd to program the pwm ramp. 9 lgnd signal ground and ic substrate connection 10 vcc power for internal circuitry 11 vccl power for low-side gate driver 12 gatel low-side gate driver output and input to g ateh non-overlap comparator 13 pgnd return for gate drivers 14 gateh high-side gate driver output and input to gatel non-overlap comparator 15 vcch power for high-side gate driver 16 csin+ non-inverting input to the current sense a mplifier 17 csin- inverting input to the current sense ampli fier and also non- inverting input to the ovp comparator 18 phsflt open collector output of the phase fault comparator. drives low if phase current is unable to match the level of the share bus due to a n external fault. connect external pull-up. 19 dacin reference voltage input from the control i c and inverting input to the ovp comparator. current sensing and pwm operation refer enced to this pin. 20 biasin system reference voltage for internal cir cuitry downloaded from: http:///
ir3086apbf page 6 of 33 may 13, 2009 system theory of operation xphase tm architecture the xphase tm architecture is designed for multiphase interleave d buck converters which are used in applications requiring small size, design flexibility, low volta ge, high current and fast transient response. the a rchitecture can control converters of any phase number where flexib ility facilitates the design trade-off of multiphas e converters. the scalable architecture can be applied to other a pplications which require high current or multiple output voltages. as shown in figure 1, the xphase tm architecture consists of a control ic and a scalab le array of phase converters each using a single phase ic. the control ic commun icates with the phase ics through a 5-wire analog b us, i.e. bias voltage, phase timing, average current, error amplifier output, and vid voltage. the control ic i ncorporates all the system functions, i.e. vid, pwm ramp oscillator , error amplifier, bias voltage, and fault protecti ons etc. the phase ic implements the functions required by the c onverter of each phase, i.e. the gate drivers, pwm comparator and latch, over-voltage protection, and current sen sing and sharing. there is no unused or redundant silicon with the xphase tm architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 ph ase operation. pcb layout is easier since the 5 wi re bus eliminates the need for point-to-point wiring betwe en the control ic and each phase. the critical gate drive and current sense connections are short and local to th e phase ics. this improves the pcb layout by loweri ng the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. rcs cin 0.1uf 0.1uf rcs ccs ccs vout+ 12v vout- vout sense- vid2 vid0 vid3 vout sense+ vid4 enable vr hot power good phase fault vid5 vid1 >> pwm control >> phase timing >> bias voltage ir3081a control ic cout control bus ir3086a phase ic input/output additional phases << current sense phase hot phase fault phase fault >> vid voltage current share current share phase hot ir3086a phase ic figure 1. system block diagram downloaded from: http:///
ir3086apbf page 7 of 33 may 13, 2009 pwm control method the pwm block diagram of the xphase tm architecture is shown in figure 2. feed-forward vo ltage mode control with trailing edge modulation is used. a high-gain wide- bandwidth voltage type error amplifier in the contr ol ic is used for the voltage control loop. an external rc circui t connected to the input voltage and ground is used to program the slope of the pwm ramp and to provide the feed-forwa rd control at each phase. the pwm ramp slope will c hange with the input voltage and automatically compensate for changes in the input voltage. the input voltag e can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage drop relat ed to changes in load current. +- 10k + - share adjust error amplifier current sense amplifier x34 x 0.91 20mv + - + - +- 10k share adjust error amplifier current sense amplifier x34 20mv x 0.91 + - + - + - + - + - dacin pwmrmp biasin rampin- rampin+ gateh scomp ishare csin+ gatel eain csin- system reference voltage enable clock pulse generator body braking comparator ramp discharge clamp pwm latch s reset dominant phase ic r pwm comparator rdrp rpwmrmp rphs2 cscomp + - rphs1 + - + - rcs rvfb + - cpwmrmp cscomp ccs rpwmrmp rcs +- cpwmrmp + - +- ccs rphs2 rphs1 + - gnd vout biasin vdac vbias dacin pwmrmp rampin+ vosns- vosns+ vosns- ishare rampin- iin vdrp eain gateh scomp csin- csin+ gatel eaout rmpout vin fb irosc system reference voltage vdac body braking comparator ramp discharge clamp enable clock pulse generator vbias regulator ifb vdrp amp 50% duty cycle ramp generator vvalley vpeak error amp r s reset dominant pwm latch phase ic cout control ic pwm comparator figure 2. pwm block diagram frequency and phase timing control an oscillator with programmable frequency is locate d in the control ic. the output of the oscillator i s a 50% duty cycle triangle waveform with peak and valley voltag es of approximately 5v and 1v respectively. this si gnal is used to program both the switching frequency and phase t iming of the phase ics. the phase ic is programmed by resistor divider r phs1 and r phs2 connected between the vbias reference voltage and the phase ic lgnd pin. a comparator in the phase ics detects the crossing of the oscillator waveform over the voltage generated by the resistor divider and triggers a clock pulse that st arts the pwm cycle. the peak and valley voltages tr ack the vbias voltage reducing potential phase ic timing errors. figure 3 shows the phase timing for an 8 phase conv erter. note that both slopes of the triangle waveform can be us ed for phase timing by swapping the rmpin+ and rmpi n? pins, as shown in figure 2. downloaded from: http:///
ir3086apbf page 8 of 33 may 13, 2009 ramp (from control ic) clk1 vvalley (1.00v) phase ic clock pulses vphase1&8 (1.5v) vphase3&6 (3.5v) vphase2&7 (2.5v) vphase4&5 (4.5v) vpeak (5.0v) clk2 50% ramp duty cycle clk3 clk4 clk5 clk6 clk7 clk8 slope = 80mv / % dc slope = 1.6mv / ns @ 200khz slope = 8.0mv / ns @ 1mhz figure 3. 8 phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon receiving a clock pulse, the pwm latch is set; the pwmrmp voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the non- overlap time. when the pwmrmp voltage exceeds the e rror amplifier?s output voltage, the pwm latch is r eset. this turns off the high side driver and turns on th e low side driver after the non-overlap time; it ac tivates the ramp discharge clamp, which quickly discharges the pwmrmp capacitor to the vdac voltage of the control ic un til the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go to 100% duty cycle in response to a load s tep increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the co mmon mode input range of the pwm comparator results in 100% d uty cycle regardless of the voltage of the pwm ramp . this arrangement guarantees the error amplifier is alway s in control and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease whi ch is appropriate given the low output to input vol tage ratio of most systems. the inductor current will increase mu ch more rapidly than decrease in response to load t ransients. this control method is designed to provide ?single cycle transient response? where the inductor curren t changes in response to load transients within a single switchi ng cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an additional advantage of the architecture is that differences in ground or input voltage at the phases have no effec t on operation since the pwm ramps are referenced t o vdac. figure 4 depicts pwm operating waveforms under vari ous conditions. downloaded from: http:///
ir3086apbf page 9 of 33 may 13, 2009 phase ic clock pulse eain vdac pwmrmp gateh gatel steady-state operation duty cycle increase due to load increase duty cycle decrease due to vin increase (feed-forward) duty cycle decrease due to load decrease (body braking) or fault (vcc uv, vccvid uv, ocp, vid=11111x) steady-state operation 91% vdac figure 4. pwm operating waveforms body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; o min max slew v i i l t ) (* ? = the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node v oltage is then forced to decrease until conduction of the synchronous rectifier?s body diode occurs. this inc reases the voltage across the inductor from vo to v o + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t + ? = ) (* since the voltage drop in the body diode is often h igher than output voltage, the inductor current sle w rate can be increased by 2x or more. this patent pending techni que is referred to as ?body braking tm ? and is accomplished through the ?body braking tm comparator? located in the phase ic. if the error amplifier?s output voltage drops below 91% of the vdac voltage this comparator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connecting a resi stor and a capacitor in parallel with the inductor and measuring the voltage across the capacitor, as shown in figur e 5. the equation of the sensing network is, cs cs l l cs cs l cs c sr sl r si c sr s v s v + + = + = 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component o f the inductor current. downloaded from: http:///
ir3086apbf page 10 of 33 may 13, 2009 figure 5. inductor current sensing and current sen se amplifier the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch curre nts. the output voltage can be positioned to meet a load lin e based on real time information. except for a sens e resistor in series with inductor, this is the only sense method that can support a single cycle transient response . other methods provide no information during either load i ncrease (low side sensing) or load decrease (high s ide sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of freq uency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all add itional sources of peak-to-average errors. current sense amplifier this is a high speed differential current sense amp lifier, as shown in figure 5. its gain decreases wi th increasing temperature and is nominally 34 at 25oc and 29 at 1 25oc (-1470 ppm/oc). this reduction of gain tends t o compensate the 3850 ppm/oc increase in inductor dcr . since in most designs the phase ic junction is ho tter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required. the current sense amplifier can accept positive dif ferential input up to 100mv and negative up to -20m v before clipping. the output of the current sense amplifier is summed with the dac voltage and sent to the con trol ic and other phases through an on-chip 10k resistor connected to the ishare pin. the ishare p ins of all the phases are tied together and the voltage on the share bus represents the average current being delivered to t he load and is used by the control ic for voltage positioning and current limit protection. average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compar ed with the share bus less a 20mv offset. if curren t in a phase is smaller than the average current, the share adjust error amplifier of the phase will activate a curren t source that reduces the slope of its pwm ramp thereby increasin g its duty cycle and output current. the crossover frequency of the current share loop can be programmed with a cap acitor at the scomp pin so that the share loop does not interact with the output voltage loop. c o l r l r cs c cs v o current sense amp csout i l v l v cs c downloaded from: http:///
ir3086apbf page 11 of 33 may 13, 2009 ir3086a theory of operation block diagram the block diagram of the ir3086a is shown in fig. 6 , and specific features are discussed in the follow ing sections. vcc vdac biasin scomp vdac 20mv rampslope adjust + - voltageproportional to absolute temperature enable faultcomparator + - + - +- + - +- +- + - + - 10k + - + - + - + - +- + - rmpin+ vcc eain rmpin- scomp pwmrmp ishare gateh lgnd biasin pgnd vcch vccl csin+ gatel phsflt vrhot hotset csin- dacin internalcircuit bias shareadjust error amp clockpulse generator rampcomparator systemreference voltage body brakingcomparator r s dominant pwmcomparator reset pwmlatch enable ovpcomparator 2v x34 currentsense amp gatenon-overlap comparators x 0.91 125mv rampdischarge clamp vdac + + vrhotcomparator figure 6 ? ir3086a block diagram tri-state gate drivers the gate drivers can deliver up to 3a peak current. an adaptive non-overlap circuit monitors the volta ge on the gateh and gatel pins to prevent mosfet shoot-throug h current while minimizing body diode conduction. an enable signal is provided by the control ic to t he phase ic without the addition of a dedicated sig nal line. the error amplifier output of the control ic drives low in response to any fault condition such as input u nder voltage or output overload. the ir3086a body braking tm comparator detects this and drives both gate outpu ts low. this tri- state operation prevents negative inductor current and negative output voltage during power-down. the gate drivers revert to a high impedance ?off? s tate if vccl and vcch supply voltages are below the normal operating range. an 80k resistor is connected across the gateh/gatel and p gnd pins to prevent the gateh/gatel voltage from rising due to leakage or o ther causes under these conditions. over voltage protection (ovp) the ir3086a includes over-voltage protection that t urns on the low side mosfet to protect the load in the event of a shorted high-side mosfet or connection of the con verter output to an excessive output voltage. a com parator monitors the voltage at the csin- pin which is usua lly connected directly to the converter output. if the voltage exceeds the dacin voltage plus 125mv typical (100mv minimum and 160mv maximum) the gatel pin drives high. the ovp circuit overrides the normal pwm oper ation and will fully turn-on the low side mosfet wi thin approximately 150ns. the low side mosfet will remai n on until the over-voltage condition ceases. downloaded from: http:///
ir3086apbf page 12 of 33 may 13, 2009 when designing for ovp the overall system must be c onsidered. in many cases the over-current protectio n of the ac-dc or dc-dc converter supplying the multiphase c onverter will be triggered thus providing effective protection without damage as long as all pcb traces and compon ents are sized to handle the worst-case maximum cur rent. if this is not possible a fuse can be added in the inp ut supply to the multiphase converter. one scenario to be careful of is where the input voltage to the multiphase con verter may be pulled below the level where the ics can provide adequate voltage to the low side mosfet thus defeat ing ovp. dynamic changes in the vid code to a lower output v oltage may trigger ovp. for example; a 250mv decrea se in output voltage combined with a light load condition will cause the low side mosfets to turn on and int erfere with body braking tm . this will not cause a problem, however, as body b raking tm will resume once the output voltage is less than 125mv above the vid voltage. since csin- pin is also used as the inductor curren t sensing input, it is usually connected to the loc al converter output, which may be far away from the load of the multiphase converter. excessive distribution impeda nce between the converter and load may trigger ovp duri ng normal operation. if the voltage drop across the distribution impedance exceeds the minimum ovp comparator thresh old of 100mv plus vid offset and voltage positionin g, the ir3086a can not be used. the ir3088 phase ic withou t ovp should be used instead in applications with e xcessive distribution impedance and very small or no avp. fo r example, a converter having 25mv of vid offset, 1 25mv of avp at full load, and 100mv of drop in the distribu tion path at full load would be ok, since 100mv + 2 5mv + 125mv = 250mv which is greater than the 100mv drop. howev er, a converter having 25mv of vid offset, no avp, and 130mv of drop in the distribution path would requir e ir3088, since 100mv + 25mv + 0mv = 125mv which is smaller than the 130mv drop. converter with programmable higher output voltage t han vid voltage may also trigger ovp during normal operation, and ir3088 should be used to replace ir3 086a. thermal monitoring (vrhot) the ir3086a senses its own die temperature and prod uces a voltage at the input of the vrhot comparator that is proportional to temperature. an external resistor d ivider connected from vbias to the hotset pin and g round can be used to program the thermal trip point of the vr hot comparator. the vrhot pin is an open-collector output and should be pulled up to a voltage source through a resistor. if the thermal trip point is reached t he vrhot output drives low. phase fault it is possible for multiphase converters to appear to be working correctly with one or more phases not functioning. the output voltage can still be regulated and the f ull load current may still be delivered. however, t he remaining phase(s) will be stressed far beyond their intended design limits and are likely to fail. loss of a ph ase can occur due to poor solder connections or mounting during the m anufacturing process, or can occur in the field. th e most common failure mode of a buck converter is failure of the high side mosfet. the ir3086a has the ability to detect if a phase st ops switching and can provide this information to t he system through the phsflt output pin. if a phase stops swi tching its output current will drop to zero and the output of the current sense amplifier will be the dacin voltage. the share adjust amplifier reacts to this by increa sing the ramp slope adjust current until it exceeds the externall y programmable pwm ramp bias current. this will cau se the voltage at the pwmrmp pin to drop below its normal operating range. the fault comparator trips and dri ves the phsflt output to ground when the voltage on the pwm rmp pin falls below 91% of the dacin voltage. phsfl t is an open-collector output and should be pulled up to a voltage source through a resistor. downloaded from: http:///
ir3086apbf page 13 of 33 may 13, 2009 application information rcs+ dbst cbst rcs+ dbst cbst vgate rgate dgate qgate rcs+ dbst cbst rvcc 20krbiasin rdrp cvccl rphase31 rphase62 cpwmrmp cvcc cin ccs+ cscomp rocset cin rcs- ccs- rcs- rphase13 cpwmrmp cin rpwmrmp rdrp1 rvcc ccs+ rphase23 ccs+ cvcc cpwmrmp rphase21 rcs- 0.1uf cvcc rvcc dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic rphase32 0. 1uf cscomp rphase22 cscomp ccs- 20krbiasin rpwmrmp ccs- cvccl cvccl l cscomp dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic cdrp dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic rphase33 rvcc cvdac cvcc 20krbiasin rphase42 ccp1 ccs- rbbfb rcs+ rvdac rpwmrmp l ccs- 20krbiasin cin rphase63 rphase52 rshare ccs- ccs+ l cfb rcs- rfb 10 ohm rvcc cscomp rphase51 cvcc cin cvcc rphase12 rcs- 20krbiasin cpwmrmp dacin 19 biasi n 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic cpwmrmp cvccl rosc l rfb1 rphase43 rphase53 rcs+ dbst dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic ccp cbst rphase11 ccs+ rcs+ rphase41 rvcc rphase61 rpwmrmp dacin 19 bi asin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic cpwmrmp rcp cvcc l rcs- rvcc 20krbiasin cvccl l rbbdrp rpwmrmp cvccl oscds 1 vid5 2 vid0 3 vid1 4 vid2 5 vid3 6 vid4 7 pwrgd 26 trm1 8 trm2 9 vosns- 10 trm3 11 trm4 12 vdac 14 ss/del 25 rosc 13 enable 28 rmpout 24 lgnd 23 vcc 22 vbias 21 bbfb 20 eaout 19 18 fb vdrp 17 iin 16 ocset 15 n/c 27 ir3081a control ic css/del rpwmrmp cin cscomp ccs+ phase fault vrhot powergood vout sense- vout sense+ vout+ enable vout- vid4 vid0 vid5 vid2 vid1 vid3 12v distribution impedance cout rcs+ dbst cbst rcs+ dbst cbst figure 7. ir3081a/ir3086a six-phase vrm/evrd 10 co nverter downloaded from: http:///
ir3086apbf page 14 of 33 may 13, 2009 design procedures ? ir3081a and ir3086a chipset ir3081a external components oscillator resistor rosc the oscillator of ir3081a generates a triangle wave form to synchronize the phase ics, and the switchin g frequency of the each phase converter equals the oscillator f requency, which is set by the external resistor r osc according to the curve in figure 13 of ir3081a data sheet. soft start capacitor c ss/del because the capacitor c ss/del programs four different time parameters, i.e. soft start delay time, soft start time, over-current latch delay time, and power good delay time, they should be considered together while cho osing c ss/del . the ss/del pin voltage controls the slew rate of th e converter output voltage, as shown in figure 10 o f ir3081a. after the enable pin voltage rises above 0.6v, ther e is a soft-start delay time t ssdel, after which the error amplifier output is released to allow the soft start. the sof t start time t ss represents the time during which converter voltage rises from zero to v o. t ss can be programmed by an external capacitor, which is determined by equation (1). o ss o ss chg del ss v t v t i c * 10* 70 * 6 / ? = = (1) once c ss/del is chosen, the soft start delay time t ssdel, the over-current fault latch delay time t ocdel , and the delay time t vccpg from output voltage (v o ) in regulation to power good are fixed and shown i n equations (2), (3) and (4) respectively. 6 / / 10*70 3.1* 3.1* ? = = del ss chg del ss ssdel c i c t (2) 6 / / 10*40 115 .0* 115 .0* ? = = del ss ocdischg del ss ocdel c i c t (3) 6 / / 10*70 )3.1 735 .3(* )3.1 065 .0 8.3(* ? ? ? = ? ? ? = o del ss chg o del ss vccpg v c i v c t (4) vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdac down-slope sr down can be programmed by the external capacitor c vdac as defined in equation (5), where i sink is the sink current of vdac pin as shown in figure 15 of ir3081a data sheet. the resistor r vdac is used to compensate vdac circuit and is determin ed by equation (6). the slew rate of vdac up- slope sr up is proportional to that of vdac down-slope and is given by equation (7), where i source is the source current of vdac pin as shown in figure15 of ir3081a data sheet. down sink vdac sr i c = (5) 2 15 10 2.3 5.0 vdac vdac c r ? ? + = (6) vdac source up c i sr = (7) downloaded from: http:///
ir3086apbf page 15 of 33 may 13, 2009 over current setting resistor r ocset the inductor dc resistance is utilized to sense the inductor current. the copper wire of inductor has a constant temperature coefficient of 3850 ppm/c, and therefo re the maximum inductor dcr can be calculated from equation (8), where r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room temperature t_ room respectively. )] ( 10* 3850 1[ _ 6 _ _ room max l room l max l t t r r ? ? + ? = ? (8) the current sense amplifier gain decreases with tem perature at the rate of 1470 ppm/c, which compensa tes part of the inductor dcr increase. the phase ic die temp erature is only a couple of degrees celsius higher than the pcb temperature due to the low thermal impedance of mlpq package. the minimum current sense amplifier gain at the maximum phase ic temperature t ic_max is calculated from equation (9). )] ( 10* 1470 1[ _ 6 _ _ room max ic room cs min cs t t g g ? ? ? ? = ? (9) the total input offset voltage (v cs_tofst ) of current sense amplifier in phase ics is the su m of input offset (v cs_ofst) of the amplifier itself and that created by the am plifier input bias currents flowing through the cur rent sense resistors r cs+ and r cs- . ? ? + + ? ? ? + = cs csin cs csin ofst cs tofst cs r i r i v v _ _ (10) the over current limit is set by the external resis tor r ocset as defined in equation (11), where i limit is the required over current limit. i ocset, the bias current of ocset pin, changes with switch ing frequency setting resistor r osc and is determined by the curve in figure 14 of ir30 81a data sheet. k p is the ratio of inductor peak current over average current in each phase and is calculated fro m equation (12). ocset min cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1( [ _ _ _ ? + + ? ? = (11) n i f v l v v v k o sw i o o i p / )2 /( ) ( ? ? ? ? ? = (12) no load output voltage setting resistor r fb and adaptive voltage positioning resistor r drp a resistor between fb pin and the converter output is used to create output voltage offset v o_nlofst, which is the difference between v dac voltage and output voltage at no load condition. a daptive voltage positioning further lowers the converter voltage by r o *i o, where r o is the required output impedance of the converter. r fb is not only determined by i fb , the current flowing out of fb pin as shown in fig ure 14 of ir3081a data sheet, but also affected by the adaptive voltage positioni ng resistor r drp and total input offset voltage of current sense amplifiers. r fb and r drp are determined by (13) and (14) respectively. max l fb o tofst cs nlofst o max l fb r i r n v v r r _ _ _ _ ? ? ? ? ? = (13) o min cs max l fb drp r n g r r r ? ? ? = _ _ (14) body braking tm related resistors r bbfb and r bbdrp the body braking tm during dynamic vid can be disabled by connecting b bfb pin to ground. if the feature is enabled, resistors r bbfb and r bbdrp are needed to restore the feedback voltage of the e rror amplifier after dynamic vid step down. usually r bbfb and r bbdrp are chosen to match r fb and r drp respectively . downloaded from: http:///
ir3086apbf page 16 of 33 may 13, 2009 ir3086a external components pwm ramp resistor r pwmrmp and capacitor c pwmrmp pwm ramp is generated by connecting the resistor r pwmrmp between a voltage source and pwmrmp pin as well as the capacitor c pwmrmp between pwmrmp and lgnd. choose the desired pwm ra mp magnitude v ramp and the capacitor c pwmrmp in the range of 100pf and 470pf, and then calculate the resistor r pwmrmp from equation (15). to achieve feed-forward voltage mode control, the resistor r ramp should be connected to the input of the converter. )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? = (15) inductor current sensing capacitor c cs+ and resistors r cs+ and r cs- the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs+ and capacitor c cs+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore th e voltage across the capacitor c cs+ represents the inductor current. if the two time c onstants are not the same, the ac component of the capacitor voltage is different fro m that of the real inductor current. the time const ant mismatch does not affect the average current sharing among t he multiple phases, but affect the current signal i share as well as the output voltage during the load current trans ient if adaptive voltage positioning is adopted. measure the inductance l and the inductor dc resist ance r l . pre-select the capacitor c cs+ and calculate r cs+ as follows. + + = cs l cs c rl r (16) the bias current flowing out of the non-inverting i nput of the current sense amplifier creates a volta ge drop across r cs+, which is equivalent to an input offset voltage of t he current sense amplifier. the offset affects the accuracy of converter current signal ishare as well as the accu racy of the converter output voltage if adaptive vo ltage positioning is adopted. to reduce the offset voltag e, a resistor r cs- should be added between the amplifier inverting input and the converter output . the resistor r cs- is determined by the ratio of the bias current from the non-inverting input and the bias current from the inverting input . + ? + ? ? = cs csin csin cs r i i r (17) if r cs- is not used, r cs+ should be chosen so that the offset voltage is sma ll enough. usually r cs+ should be less than 2 k and therefore a larger c cs+ value is needed. over temperature setting resistors r hotset1 and r hotset2 the threshold voltage of vrhot comparator is propor tional to the die temperature t j (oc) of phase ic. determine the relationship between the die temperature of pha se ic and the temperature of the power converter ac cording to the power loss, pcb layout and airflow etc, and the n calculate hotset threshold voltage corresponding to the allowed maximum temperature from equation (18). 241 .1 * 10*73.4 3 + = ? j hotset t v (18) there are two ways to set the over temperature thre shold, central setting and local setting. in the ce ntral setting, only one resistor divider is used, and the setting voltage is connected to hotset pins of all the phas e ics. to reduce the influence of noise on the accuracy of ov er temperature setting, a 0.1uf capacitor should be placed next to hotset pin of each phase ic. in the local settin g, a resistor divider per phase is needed, and the setting voltage is connected to hotset pin of each phase. the 0.1uf decoupling capacitor is not necessary. use vbias a s the reference voltage. if r hotset1 is pre-selected, r hotset2 can be calculated as follows. hotset bias hotset hotset hotset v v v r r ? ? = 1 2 (19) downloaded from: http:///
ir3086apbf page 17 of 33 may 13, 2009 phase delay timing resistors r phase1 and r phase2 the phase delay of the interleaved multiphase conve rter is programmed by the resistor divider connecte d at rmpin+ or rmpin- depending on which slope of the os cillator ramp is used for the phase delay programmi ng of phase ic, as shown in figure 3. if the upslope is used, rmpin+ pin of the phase ic should be connected to rmpout pin of the control ic and rmpin- pin should be connected to the resistor divi der. when rmpout voltage is above the trip voltage at rmpin- pin, the pwm latch is set. gatel becomes low , and gateh becomes high after the non-overlap time . if down slope is used, rmpin- pin of the phase ic s hould be connected to rmpout pin of the control ic and rmpin+ pin should be connected to the resistor divi der. when rmpout voltage is below the trip voltage at rmpin- pin, the pwm latch is set. gatel becomes low , and gateh becomes high after the non-overlap time . use vbias voltage as the reference for the resistor divider since the oscillator ramp magnitude from c ontrol ic tracks vbias voltage. try to avoid both edges of th e oscillator ramp for better noise immunity. determ ine the ratio of the programming resistors corresponding to the d esired switching frequencies and phase numbers. if the resistor r phasex1 is pre-selected, the resistor r phasex2 is determined as: phasex phasex phasex phasex ra r ra r ? ? = 1 1 2 (20) combined over temperature and phase delay setting r esistors r phase1 , r phase2 and r phase3 the over temperature setting resistor divider can b e combined with the phase delay resistor divider to save one resistor per phase. calculate the hotset threshold voltage v hotset corresponding to the allowed maximum temperature f rom equation (18). if the over temperature setting volt age is lower than the phase delay setting voltage, vbias*ra phasex , connect rmpin+ or rmpin- pin between r phasex1 and r phasex2, and connect hotset pin between r phasex2 and r phasex3 . pre-select r phasex1 , ) 1( *) ( 1 2 phasex bias phasex hotset bias phasex phasex ra v r v v ra r ? ? ? ? = (21) ) 1(* 1 3 phasex bias phasex hotset phasex ra v r v r ? ? = (22) if the over temperature setting voltage is higher t han the phase delay setting voltage, vbias*ra phasex , connect hotset pin between r phasex1 and r phasex2, and connect rmpin+ or rmpin- between r phasex2 and r phasex3 . pre-select r phasex1 , hotset bias phasex bias phasex hotset phasex v v r v ra v r ? ? ? ? = 1 2 ) ( (23) hotset bias phasex bias phasex phasex v v r v ra r ? ? = 1 3 * (24) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a 0.1uf to 1uf capacitor is needed for the bootstrap circuit. decoupling capacitors for phase ic 0.1uf-1uf decoupling capacitors are required at vcc and vccl pins of phase ics. downloaded from: http:///
ir3086apbf page 18 of 33 may 13, 2009 voltage loop compensation the adaptive voltage positioning (avp) is usually a dopted in the computer applications to improve the transient response and reduce the power loss at heavy load. l ike current mode control, the adaptive voltage posi tioning loop introduces extra zero to the voltage loop and split s the double poles of the power stage, which make t he voltage loop compensation much easier. resistors r fb and r drp are chosen according to equations (13) and (14), a nd the selection of compensation types depends on the output capacitors used in the conver ter. for the applications using electrolytic, polym er or al- polymer capacitors and running at lower frequency, type ii compensation shown in figure 8(a) is usuall y enough. while for the applications using only ceramic capac itors and running at higher frequency, type iii com pensation shown in figure 8(b) is preferred. for applications where avp is not required, the com pensation is the same as for the regular voltage mo de control. for converter using polymer, al-polymer, and cerami c capacitors, which have much higher esr zero frequ ency, type iii compensation is required as shown in figur e 8(b) with r drp and c drp removed. rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 (a) type ii compensation (b) type iii compensation figure 8. voltage loop compensation network type ii compensation for avp applications determine the compensation at no load, the worst ca se condition. choose the crossover frequency fc bet ween 1/10 and 1/5 of the switching frequency per phase. assum e the time constant of the resistor and capacitor a cross the output inductors matches that of the inductor, and determine r cp and c cp from equations (25) and (26), where l e and c e are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. 2 2 ) * * * 2( 1 * ) 2( c c o pwmrmp fb e e c cp r c f v v r c l f r + ? ? ? ? ? = (25) cp e e cp r c l c ? ? = 10 (26) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. type iii compensation for avp applications determine the compensation at no load, the worst ca se condition. assume the time constant of the resis tor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by equations (27) and (28), where r le is the equivalent resistance of inductor dcr. le fb cs e drp c r r g c r f ? ? = * * 2 1 (27) downloaded from: http:///
ir3086apbf page 19 of 33 may 13, 2009 180 )5.0 tan( 90 1 ? ? = a c (28) choose the desired crossover frequency fc around fc 1 estimated by equation (27) or choose fc between 1 /10 and 1/5 of the switching frequency per phase, and selec t the components to ensure the slope of close loop gain is -20db /dec around the crossover frequency. choose resisto r r fb1 according to equation (29), and determine c fb and r drp from equations (30) and (31). fb fb r r 2 1 1 = to fb fb r r 3 2 1 = (29) 1 4 1 fb c fb r f c ? ? = (30) drp fb fb fb drp r c r r c ? + = ) ( 1 (31) r cp and c cp have limited effect on the crossover frequency, an d are used only to fine tune the crossover frequenc y and transient load response. determine r cp and c cp from equations (32) and (33). o pwmrmp fb e e c cp v v r c l f r ? ? ? ? ? = 2 ) 2( (32) cp e e cp r c l c ? ? = 10 (33) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. type iii compensation for non-avp applications resistor r fb is chosen according to equations (13), and resisto r r drp and capacitor c drp are not needed. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the de sired phase margin c. calculate k factor from equation (34), and deter mine the component values based on equations (35) t o (39), )]5.1 180 ( 4 tan[ + ? = c k (34) k v v f c l r r o pwmrmp c e e fb cp ? ? ? ? ? ? = 2 ) 2( (35) cp c cp r f k c ? ? = 2 (36) cp c cp r k f c ? ? ? = 2 1 1 (37) fb c fb r f k c ? ? = 2 (38) fb c fb c k f r ? ? ? = 2 1 1 (39) downloaded from: http:///
ir3086apbf page 20 of 33 may 13, 2009 current share loop compensation the crossover frequency of the current share loop s hould be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the t wo loops. a capacitor from scomp to ground is usual ly enough for the share loop compensation. choose the crossov er frequency of current share loop (f ci ) based on the crossover frequency of voltage loop (f c), and determine the c scomp , 6 _ 10*05.1* 2 *)] (* * * 2 1[* * * * * *65.0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c ? ? + = (40) where f mi is the pwm gain in the current share loop , ) (*) ( * * * dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f ? ? ? = ( 41) downloaded from: http:///
ir3086apbf page 21 of 33 may 13, 2009 design example 1 - vrm 10 2u converter specifications input voltage: v i =12 v dac voltage: v dac =1.35 v no load output voltage offset: v o_nlofst =20 mv output current: i o =105 adc maximum output current: i omax =120 adc output impedance: r o =0.91 m vcc ready to vcc power good delay: t vccpg =0-10ms soft start time: t ss =2 ms over current delay: t ocdel < 0.5ms dynamic vid down-slope slew rate: sr down =2.5mv/us over temperature threshold: t pcb =115 oc power stage phase number: n=6 switching frequency: f sw =400 khz output inductors: l=220 nh, r l =0.47 m output capacitors: al-polymer, c=560uf, r c = 7m , number cn=10 ir3081a external components oscillator resistor rosc once the switching frequency is chosen, r osc can be determined from the curve in figure 13 of i r3081a data sheet. for switching frequency of 400khz per phase, choose r osc =30.1k soft start capacitor c ss/del determine the soft start capacitor from the require d soft start time. uf v t i c o ss chg del ss 1.0 10*20 35.1 10*2 10*70 3 3 6 / = ? ? = ? = ? ? ? the soft start delay time is ms i c t chg del ss ssdel 86.1 10*70 3.1 10*1.0 3.1 6 6 / = ? = ? = ? ? the power good delay time is ms i v c t chg o del ss vccpg 58.1 10*70 )3.1 33.1 735 .3(* 10*1.0 )3.1 735 .3(* 6 6 / = ? ? = ? ? = ? ? over current delay time is ms i c t ocdischg del ss ocdel 29.0 10*40 115 .0* 10*1.0 115 .0* 6 6 / = = = ? ? downloaded from: http:///
ir3086apbf page 22 of 33 may 13, 2009 vdac slew rate programming capacitor c vdac and resistor r vdac from figure 15 of ir3081a data sheet, the sink curr ent of vdac pin corresponding to 400khz (r osc =30.1k ) is 76ua. calculate the vdac down-slope slew-rate progr amming capacitor from the required down-slope slew rate. nf sr i c down sink vdac 4.30 10/ 10*5.2 10*76 6 3 6 = = = ? ? ? , choose c vdac =33nf calculate the programming resistor. ? = + = + = ? ? ? 5.3 ) 10*33( 10*2.3 5.0 10*2.3 5.0 29 15 2 15 vdac vdac c r from figure 15 or ir3081a data sheet, the source cu rrent of vdac pin is 110ua. the vdac up-slope slew rate is us mv c i sr vdac source up / 3.3 10*33 10* 110 9 6 = = = ? ? over current setting resistor r ocset the room temperature is 25oc and the target pcb tem perature is 100 oc. the phase ic die temperature is about 1 oc higher than that of phase ic, and the inductor t emperature is close to pcb temperature. calculate inductor dc resistance at 100 oc, ? = ? ? + ? = ? ? + ? = ? ? ? m t t r r room max l room l max l 61.0 )]25 100 ( 10* 3850 1[ 10*47.0 )] ( 10* 3850 1[ 6 3 _ 6 _ _ the current sense amplifier gain is 34 at 25oc, and its gain at 101oc is calculated as, 2.30 )] 25 101 ( 10* 1470 1[ 34 )] ( 10* 1470 1[ 6 _ 6 _ _ = ? ? ? ? = ? ? ? ? = ? ? room max ic room cs min cs t t g g set the over current limit at 135a. from figure 14 of ir3081a data sheet, the bias current of ocset pi n (i ocset ) is 41ua with r osc =30.1k . the total current sense amplifier input offset vo ltage is 0.55mv, which includes the offset created by the current sense amplifier input resistor mismatch. calculate constant k p, the ratio of inductor peak current over average cur rent in each phase, 3.0 6/ 135 )2 10* 400 12 10* 220 /( 33.1)33.1 12( / )2 /( ) ( 3 9 = ? ? ? ? ? = ? ? ? ? ? = ? n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n r r / ] ) 1( [ _ _ _ ? + + ? ? = ? = ? + ? ? = ? ? ? k 3.13 ) 10*41 /(2.30 ) 10*55.0 3.1 10*61.0 6 135 ( 6 3 3 no load output voltage setting resistor r fb and adaptive voltage positioning resistor r drp from figure 14 of ir3081a data sheet, the bias curr ent of fb pin is 41ua with r osc =30.1k . ? = ? ? ? ? ? = ? ? ? ? ? = ? ? ? ? ? ? 365 10* 61.0 10* 41 10* 91.0 6 10* 55.0 10* 20 10* 61.0 3 6 3 3 3 3 _ _ _ _ max l fb o tofst cs nlofst o max l fb r i r n v v r r ? = ? ? ? = ? ? ? = ? ? k r n g r r r o min cs max l fb drp 21.1 10*91.0 6 2.30 10*61.0 365 3 3 _ _ downloaded from: http:///
ir3086apbf page 23 of 33 may 13, 2009 body braking tm related resistors r bbfb and r bbdrp n/a. the body braking during dynamic vid is disable d. ir3081a external components pwm ramp resistor r pwmrmp and capacitor c pwmrmp set pwm ramp magnitude v pwmrmp =0.8v. choose 220pf for pwm ramp capacitor c pwmrmp , and calculate the resistor r pwmrmp , )] ln( ) [ln( pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? ? ? ? = ? = ? ? ? ? ? ? ? = ? k 1.16 )]8.0 35.1 12 ln( )35.1 12 [ln( 10* 220 10* 400 12 33.1 12 3 , choose r pwmrmp =16.2k inductor current sensing capacitor c cs+ and resistors r cs+ and r cs- choose c cs+ =47nf, and calculate r cs+, ? = = = ? ? ? + + k c rl r cs l cs 0.10 10*47 ) 10*47.0/( 10* 220 9 3 9 the bias currents of csin+ and csin- are 0.25ua and 0.4ua respectively. calculate resistor r cs- , ? = ? = ? = + ? k r r cs cs 2.6 10*0.10 4.0 25.0 4.0 25.0 3 , choose r cs- =6.19k over temperature setting resistors r hotset1 and r hotset2 use central over-temperature setting and set the te mperature threshold at 115 oc, which corresponds to the ic die temperature of 116 oc. calculate the hotset thresho ld voltage corresponding to the temperature thresho lds. v t v j hotset 79.1 241 .1 116 10*73.4 241 .1 * 10*73.4 3 3 = + ? = + = ? ? pre-select r hotset1 =10.0k , ? = ? ? = ? ? = k v v v r r hotset bias hotset hotset hotset 57.3 79.1 8.6 79.1 10*10 3 1 2 phase delay timing resistors r phase1 and r phase2 use central over-temperature setting and set the te mperature threshold at 115 oc, which corresponds to the ic die temperature of 116 oc. calculate the hotset thresho ld voltage corresponding to the temperature thresho lds. the phase delay resistor ratios for phases 1 to 6 a t 400khz of switching frequencies are ra phase1 =0.628, ra phase2 =0.415, ra phase3 =0.202, ra phase4 =0.246, ra phase5 =0.441 and ra phase6 =0.637 starting from down- slope. pre-select r phase11 =r phase21 =r phase31 =r phase41 =r phase51 = r phase61 =10k , ? = ? ? = ? ? = k r ra ra r phase phase phase phase 9.16 10*10 628 .0 1 628 .0 1 3 11 1 1 12 r phase22 =7.15k , r phase32 =2.55k , r phase42 =3.24k , p phase52 =7.87k , r phase62 =17.4k downloaded from: http:///
ir3086apbf page 24 of 33 may 13, 2009 bootstrap capacitor c bst choose c bst =0.1uf decoupling capacitors for phase ic and power stage choose c vcc =0.1uf, c vccl =0.1uf voltage loop compensation type ii compensation is used for the converter with al-polymer output capacitors. choose the crossover frequency fc=40khz, which is 1/10 of the switching frequency per phase, and determine rcp and c cp . ? = + ? ? ? ? ? ? ? ? ? ? ? = + ? ? ? ? ? = ? ? ? ? ? k r c f v v r c l f r c c o ramp fb e e c cp 0.2 ) 10*7* 10* 560 * 10*40* 2(1 *) 10 20 35.1( 8.0 365 )10 10 560 ()6/ 10 220 ( ) 10 40 2( ) * * * 2(1 * ) 2( 23 6 3 3 6 9 23 2 2 nf r c l c cp e e cp 71 10 0.2 )10* 10 560 ()6/ 10 220 ( 10 10 3 6 9 = ? ? ? ? ? = ? ? = ? ? , choose c cp =68nf choose c cp1 =47pf to reduce high frequency noise. current share loop compensation the crossover frequency of the current share loop f ci should be at least one decade lower than that of t he voltage loop f c . choose the crossover frequency of current share l oop f ci =4khz , and calculate c scomp , 011 .0 )35.1 12(*)35.1 8.0 12( 8.0* 10* 400 * 10* 220 * 10*2.16 ) (*) ( * * * 3 12 3 = ? ? ? = ? ? ? = ? dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10*05.1* 2 *)] (* * * 2 1[* * * * * *65.0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c ? ? + = 6 3 4 4 6 3 3 3 10*05.1* 10*4 2) 10*1.9* 105 33.1( 011 .0*] 105 ) 10*1.9* 105 33.1(*10* 10* 560 * 10*4* 2 1[*)6 10*47.0(*34* 105 *12* 10*2.16*65.0 ? ? ? ? + = ? ? ? ? nf 4.31 = choose c scomp =33nf. downloaded from: http:///
ir3086apbf page 25 of 33 may 13, 2009 design example 2 - evrd 10 high frequency all-ceram ic converter specifications input voltage: v i =12 v dac voltage: v dac =1.3 v no load output voltage offset: v o_nlofst =20 mv output current: i o =105 adc maximum output current: i omax =120 adc output impedance: r o =0.91 m vcc ready to vcc power good delay: t vccpg =0-10ms soft start time: t ss =2.9ms over current delay: t ocdel < 0.5ms dynamic vid down-slope slew rate: sr down =2.5mv/us over temperature threshold: t pcb =115 oc power stage phase number: n=6 switching frequency: f sw =800 khz output inductors: l=100 nh, r l =0.5 m output capacitors: ceramic, c=22uf, r c = 2m , number cn=62 ir3081a external components oscillator resistor rosc once the switching frequency is chosen, r osc can be determined from the curve in figure 13 of i r3081a data sheet. for switching frequency of 800khz per phase, choose r osc =13.3k soft start capacitor c ss/del determine the soft start capacitor from the require d soft start time. uf v t i c o ss chg del ss 16.0 10*20 3.1 10*3 10*70 3 3 6 / = ? ? = ? = ? ? ? , choose c ss/del =0.15uf the soft start delay time is ms i c t chg del ss ssdel 8.2 10*70 3.1 10*15.0 3.1 6 6 / = ? = ? = ? ? the power good delay time is ms i v c t chg o del ss vccpg 4.2 10*70 )3.1 33.1 735 .3(* 10*15.0 )3.1 735 .3(* 6 6 / = ? ? = ? ? = ? ? over current delay time is ms i c t ocdischg del ss ocdel 43.0 10*40 115 .0* 10*15.0 115 .0* 6 6 / = = = ? ? vdac slew rate programming capacitor c vdac and resistor r vdac from figure 15 of ir3081a data sheet, the sink curr ent of vdac pin corresponding to 800khz (r osc =13.3k ) is 170ua. calculate the vdac down-slope slew-rate prog ramming capacitor from the required down-slope slew rate. downloaded from: http:///
ir3086apbf page 26 of 33 may 13, 2009 nf sr i c down sink vdac 68 10/ 10*5.2 10* 170 6 3 6 = = = ? ? ? calculate the programming resistor. ? = + = + = ? ? ? 2.1 ) 10*68( 10*2.3 5.0 10*2.3 5.0 29 15 2 15 vdac vdac c r from figure 15 of ir3081a data sheet, the source cu rrent of vdac pin is 250ua. the vdac up-slope slew rate is us mv c i sr vdac source up / 7.3 10*68 10* 250 9 6 = = = ? ? over current setting resistor r ocset the room temperature is 25oc and the target pcb tem perature is 100 oc. the phase ic die temperature is about 1 oc higher than that of phase ic, and the inductor t emperature is close to pcb temperature. calculate inductor dc resistance at 100 oc, ? = ? ? + ? = ? ? + ? = ? ? ? m t t r r room max l room l max l 64.0 )]25 100 ( 10* 3850 1[ 10*5.0 )] ( 10* 3850 1[ 6 3 _ 6 _ _ the current sense amplifier gain is 34 at 25oc, and its gain at 101oc is calculated as, 2.30 )] 25 101 ( 10* 1470 1[ 34 )] ( 10* 1470 1[ 6 _ 6 _ _ = ? ? ? ? = ? ? ? ? = ? ? room max ic room cs min cs t t g g set the over current limit at 135a. from figure 14 of ir3081a data sheet, the bias current of ocset pi n (i ocset ) is 90ua with r osc =13.3k . the total current sense amplifier input offset vo ltage is 0.55mv, which includes the offset created by the current sense amplifier input resistor mismatch. calculate constant k p, the ratio of inductor peak current over average cur rent in each phase, 32.0 6/ 135 )2 10* 800 12 10* 100 /( 28.1)28.1 12( / )2 /( ) ( 3 9 = ? ? ? ? ? = ? ? ? ? ? = ? n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n r r / ] ) 1( [ _ _ _ ? + + ? ? = ? = + ? ? = ? ? ? k 34.6 ) 10*90/(2.30*) 10*55.0 32.1 10*64.0 6 135 ( 6 3 3 no load output voltage setting resistor r fb and adaptive voltage positioning resistor r drp from figure 14 of ir3081a data sheet, the bias curr ent of fb pin is 90ua with r osc =13.3k . ? = ? ? ? ? = ? ? ? ? ? = ? ? ? ? ? ? 162 10*64.0* 10*90 10*91.0 6 10*55.0 10*20 10*64.0 3 6 3 3 3 3 _ _ _ _ max l fb o tofst cs nlofst o max l fb r i r n v v r r ? = ? ? = ? ? ? = ? ? 576 10*91.0 6 2.30* 10*64.0 162 3 3 _ _ o min cs max l fb drp r n g r r r body braking tm related resistors r bbfb and r bbdrp n/a. the body braking during dynamic vid is disable d. downloaded from: http:///
ir3086apbf page 27 of 33 may 13, 2009 ir3086a external components pwm ramp resistor r pwmrmp and capacitor c pwmrmp set pwm ramp magnitude v pwmrmp =0.75v. choose 100pf for pwm ramp capacitor c pwmrmp , and calculate the resistor r pwmrmp , )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? = ? = ? ? ? ? ? ? ? ? = k 2.18 )]75.0 3.1 12 ln( )3.1 12 [ln( 12 10* 100 3 10* 800 12 28.1 inductor current sensing capacitor c cs+ and resistors r cs+ and r cs- choose 47nf for capacitor c cs+, and calculate r cs+, ? = = = ? ? ? + + k c rl r cs l cs 22.4 10*47 ) 10*5.0/( 10* 100 9 3 9 the bias currents of csin+ and csin- are 0.25ua and 0.4ua respectively. calculate resistor r cs- , ? = ? = ? = + ? k r r cs cs 61.2 10*22.4 4.0 25.0 4.0 25.0 3 combined over temperature and phase delay setting r esistors r phasex1 , r phasex2 and r phasex3 the over temperature setting resistor divider is co mbined with the phase delay resistor divider. set t he temperature threshold at 115 oc, which corresponds to the ic di e temperature of 116 oc, and calculate the hotset t hreshold voltage corresponding to the temperature thresholds . v t v j hotset 79.1 241 .1 116 10*73.4 241 .1 10*73.4 3 3 = + ? = + ? = ? ? the phase delay resistor ratios for phases 1 to 6 a t 800khz of switching frequencies are ra phase1 =0.665, ra phase2 =0.432, ra phase3 =0.198, ra phase4 =0.206, ra phase5 =0.401 and ra phase6 =0.597 starting from down- slope. the over temperature setting voltage of phases 1, 2 , 5, and 6 is lower than the phase delay setting vo ltage, vbias*ra phasex. pre-select r phase11 =10k , ? = ? ? ? ? ? = ? ? ? ? = k ra v r v v ra r phasex bias phasex hotset bias phasex phasex 1.12 ) 665 .0 1(8.6 10*10 )79.1 8.6 665 .0( ) 1( *) ( 3 1 2 ? = ? ? = ? ? = k ra v r v r phasex bias phasex hotset phasex 87.7 ) 665 .0 1(*8.6 10*1.12 79.1 ) 1(* 3 1 3 r phase21 =10k , r phase22 =2.94k , r phase23 =4.64k r phase51 =10k , r phase52 =2.32k , r phase53 =4.42k r phase61 =10k , r phase62 =8.25k , r phase63 =6.49k the over temperature setting voltage of phases 3 an d 4 is higher than the phase delay setting voltage, vbias*ra phasex. pre-select r phasex1 =10k , ? = ? ? ? ? = ? ? ? ? = 887 79.1 8.6 10*10 )8.6 198 .0 79.1( ) ( 3 31 3 32 hotset bias phase bias phase hotset phase v v r v ra v r ? = ? ? ? = ? ? = k v v r v ra r hotset bias phase bias phase phase 67.2 79.1 8.6 10*10 8.6 198 .0 * 3 31 3 33 downloaded from: http:///
ir3086apbf page 28 of 33 may 13, 2009 r phase41 =10k , r phase42 =768 , r phase43 =2.80k bootstrap capacitor c bst choose c bst =0.1uf decoupling capacitors for phase ic and power stage choose c vcc =0.1uf, c vccl =0.1uf voltage loop compensation type iii compensation is used for the converter wit h only ceramic output capacitors. the crossover fre quency and phase margin of the voltage loop can be estimated a s follows. khz r r g c r f le fb cs e drp c 146 )6/ 10*5.0( 162 34 ) 10* 22 62( 2 576 2 3 6 1 = ? ? ? ? ? = ? ? ? ? = ? ? = ? ? = 63 180 )5.0 tan( 90 1 a c choose ? = ? = ? = 110 162 3 2 3 2 1 fb fb r r choose the desired crossover frequency fc (=140khz) around fc1 estimated above, and calculate nf r f c fb c fb 2.5 110 10* 140 4 1 4 1 3 1 = ? ? = ? ? = , choose c fb =5.6nf nf r c r r c drp fb fb fb drp 7.2 576 10*6.5) 110 162 ( ) ( 9 1 = ? + = ? + = ? ? = ? ? ? ? ? ? = ? ? ? ? ? = ? ? ? k v v r c l f r o ramp fb e e c cp 65.1 10*20 3.1 75.0* 162 )62 10*22()6/ 10* 100 ( ) 10* 140 2( ) 2( 3 6 9 23 2 nf r c l c cp e e cp 27 10 65.1 )62* 10*22()6/ 10* 100 ( 10 10 3 6 9 = ? ? ? = ? ? = ? ? choose c cp1 =47pf to reduce high frequency noise. current share loop compensation the crossover frequency of the current share loop f ci should be at least one decade lower than that of t he voltage loop f c . choose the crossover frequency of current share l oop f ci =3.5khz , and calculate c scomp , 011 .0 )3.1 12(*)3.1 75.0 12( 75.0* 10* 800 * 10* 100 * 10*2.18 ) (*) ( * * * 3 12 3 = ? ? ? = ? ? ? = ? dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10*05.1* 2 *)] (* * * 2 1[* * * * * *65.0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c ? ? + = 6 4 4 6 3 3 10*05.1* 3500 2) 10*1.9* 105 33.1( 011 .0*] 105 ) 10*1.9* 105 33.1(*62* 10*22* 3500 * 2 1[*)6 10*5.0(*34* 105 *12* 10*2.18*65.0 ? ? ? ? + = ? ? ? ? nf 6.20 = choose c scomp =22nf downloaded from: http:///
ir3086apbf page 29 of 33 may 13, 2009 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout, therefore minimizing the noise coupled to t he ic. dedicate at least one middle layer for a ground pl ane, which is then split into signal ground plane ( lgnd) and power ground plane (pgnd). connect pgnd to lgnd pins of each phase ic to the ground tab, which is tied to lgnd and pgnd planes respectively through vias. in order to reduce the noise coupled to scomp pin of phase ic, use a dedicated wire to connect the ca pacitor c scomp directly to lgnd pin. however, connect pwm ramp ca pacitor c pwmrmp , phase delay programming resistor r phase2 or r phase3, decoupling capacitor c vcc to lgnd plane through vias. place current sense resistors and capacitors (r cs+ , r cs- , c cs+ , and c cs- ) close to phase ic. use kelvin connection for the inductor current sense wires, bu t separate the two wires by ground polygon. the wir e from the inductor terminal to rcs- should not cross over the fast transition nodes, i.e. switching nodes, g ate drive outputs and bootstrap nodes. place the decoupling capacitors c vcc and c vccl as close as possible to vcc and vccl pins of the p hase ic respectively. place the phase ic as close as possible to the mos fets to reduce the parasitic resistance and inducta nce of the gate drive paths. place the input ceramic capacitors close to the dr ain of top mosfet and the source of bottom mosfet. use combination of different packages of ceramic capaci tors. there are two switching power loops. one loop incl udes the input capacitors, top mosfet, inductor, ou tput capacitors and the load; another loop consists of b ottom mosfet, inductor, output capacitors and the l oad. route the switching power paths using wide and shor t traces or polygons; use multiple vias for connect ions between layers. lgnd vcc vccl eain scomp gatel gateh pgnd csin+ csin- dacin biasin to signal bus ishare to inductor to pgnd plane to lgnd plane c vcc c vccl to vin to lgnd plane r pwmrmp c pwmrmp c scomp r biasin r cs+ d bst vcch c bst to gate drive voltage r phase2 r phase1 vrhot hotset rmpin- rmpin+ phsflt eain pwmrmp to top mosfet pgnd plane lgnd plane to switching node ground polygon c cs+ r cs- c cs- ground polygon to lgnd plane to bottom mosfet lgnd vcc vccl eain scomp gatel gateh pgnd csin+ csin- dacin biasin to signal bus ishare to inductor to pgnd plane to lgnd plane c vcc c vccl to vin to lgnd plane r pwmrmp c pwmrmp c scomp r biasin r cs+ d bst vcch c bst to gate drive voltage r phase2 r phase1 vrhot hotset rmpin- rmpin+ phsflt eain pwmrmp to top mosfet pgnd plane lgnd plane to switching node ground polygon c cs+ r cs- c cs- ground polygon to lgnd plane to bottom mosfet downloaded from: http:///
ir3086apbf page 30 of 33 may 13, 2009 pcb metal and component placement lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. lead land length should be equal to maximum part l ead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment an d ensure a fillet. center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) four 0.3mm diameter vias shall be placed in the pa d land spaced at 1.2mm, and connected to ground to minimize the noise effect on the ic and to transfer heat to the pcb. no pcb traces should be routed nor vias placed und er any of the 4 corners of the ic package. doing s o can cause the ic to rise up from the pcb resulting in p oor solder joints to the ic leads. downloaded from: http:///
ir3086apbf page 31 of 33 may 13, 2009 solder resist the solder resist should be pulled away from the m etal lead lands and center pad by a minimum of 0.06 mm. the solder resist mis-alignment is a maximum of 0.0 5mm and it is recommended that the lead lands are a ll non solder mask defined (nsmd). therefore, pulling the s/r 0.06mm will always ensure nsmd pads. the minimum solder resist width is 0.13mm. at the inside corner of the solder resist where the lead l and groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lea d lands from the pad land. the 4 vias in the land pad should be tented with s older resist 0.4mm diameter, or 0.1mm larger than t he diameter of the via. downloaded from: http:///
ir3086apbf page 32 of 33 may 13, 2009 stencil design the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimi ze the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain re peatable solder release. the stencil lead land apertures should therefore b e shortened in length by 80% and centered on the le ad land. the land pad aperture should be striped with 0.25m m wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. the maximum length and width of the land pad stenc il aperture should be equal to the solder resist op ening minus an annular 0.2mm pull back to decrease the in cidence of shorting the center land to the lead lan ds when the part is pushed into the solder paste. downloaded from: http:///
ir3086apbf page 33 of 33 may 13, 2009 package information: 20l mlpq (4 x 4 mm body) ? ja = 32 o c/w, jc = 3 o c/w data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on ir?s web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on. downloaded from: http:///

▲Up To Search▲

Price & Availability of IR3086AMPBF

	To Download IR3086AMPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .